Device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips typically have multilevel structures containing patterns of metal wiring layers encapsulated in an insulator. Wiring structures within a given level of wiring are separated by an intra level dielectric, while the individual wiring levels are separated from each other by layers of an inter level dielectric, Conductive vias are formed in the inter level dielectric to provide inter level contacts between the wiring traces.
Because of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact chip speed, and thus chip performance. Signal-propagation delays are due to RC time constants wherein “R” is the resistance of the on-chip wiring, and “C” is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material, and by using inter level and intra level dielectrics (ILDs) with lower dielectric constants, k.
The common terminology used to classify ILDs by their dielectric constant falls into four categories: standard k (4.5 k<10), low k (k<3.0), ultra low k (2.0 k<<2.5), and extreme low k (k<2.0). Ultra low k and extreme low k dielectrics generally tend to be porous with intentionally engineered voids in their structure. Since the lowest dielectric constant possible comprises air or vacuum (kvac=1) the industry has developed means to produce voids in the dielectric. When the void volume extends and occupies substantial contiguous regions of the gaps between the lines of wires of a chip device, one achieves an interconnect structure where these lines are nominally separated by air or vacuum as the ILD material. We employ the term “air bridge” to describe such an interconnect structure to distinguish it from structures which employ a porous ILD with void volume dispersed randomly within a nominally contiguous solid dielectric.
An example of a metal/dielectric combination for low RC interconnect structures comprises copper metal with a dielectric such as SiO2 (k˜4.0). Due to difficulties in subtractively patterning copper, copper-containing interconnect structures are typically fabricated by a damascene process. In a typical damascene process, conductive metal patterns, which are inset in a layer of dielectric, are formed by the steps of: (i) etching holes (for vias) or trenches (for wiring) into the inter level or intra level dielectric; (ii) optionally, lining the holes or trenches with one or more adhesion or diffusion barrier layers; (iii) overfilling the holes or trenches with a conductive metal wiring material such as copper, although other metals may be used in this regard such as aluminum, gold, silver, tin, alloys thereof and combinations thereof including combinations with copper and alloys of copper. This is followed by step (iv), removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric.
Commercial processes can repeat these steps until the desired number of wiring and via levels have been fabricated. Fabrication of interconnect structures by damascene processing can be substantially simplified by using a process variation known as dual damascene, in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. Dual damascene reduces the number of metal polishing steps by a factor of two, providing substantial cost savings, but requires introduction of a dual-relief pattern in the combined via and wiring level dielectric.
In a typical DD process, an inter-metal dielectric (IMD) is coated on a substrate and comprises a via level dielectric and line level dielectric. These two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer or a layered stack is optionally employed to facilitate etch selectivity and to serve as a polish stop. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and the via features which connect lines in different levels of interconnects in a multilevel stack together. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica glass (FSG) film deposited by plasma enhanced chemical vapor deposition (PECVD).
Wolf, “Introduction to Dual-Damascene Processes,” Silicon Processing For the VLSI Era, Vol. 4, pp. 674-79, Lattice Press (2004); Yen et al., U.S. Pat. No. 5,801,094; Wang et al. WO 2004/053948 A3; Woo, U.S. Pat. No. 7,015,149; Colburn, U.S. Pat. No. 7,071,097; and Gambino, et al., United States Patent Publication 20060172514, Aug. 3, 2006 also describe dual damascene processes.
Low-k alternatives to SiO2 comprise carbon-based solid materials such as diamond-like carbon (DLC), also known as amorphous hydrogenated carbon (a-C:H), fluorinated DLC (FDLC), SiCO or SiCOH compounds, and organic or inorganic polymer dielectrics. Nanoporous versions of SiO2 and the above-mentioned carbon-based materials have even lower k values, while air-gaps have the lowest k values of any material (k˜1.00). (Note that the air in the air-gap may comprise any gaseous material or vacuum.) Havemann, et al, U.S. Pat. No. 5,461,003; Grill, et al., U.S. Pat. No. 5,869,880; and Chang, et al. U.S. Pat. No. 5,559,055 describe multilayer interconnect structures incorporating air-gaps. Additionally, Wang et al. WO 2004/053948 A3 and Colburn et al. U.S. Pat. No. 6,930,034 describe methods of placing air-gaps or “air bridges” in a semiconductor chip, or semiconductor array, or wafer, or integrated circuit (IC) components.
One prior art method for forming air-gaps utilizes a sacrificial place-holder (SPH) material which is removed or extracted from beneath a solid or semi-permeable bridge layer. Examples of SPH materials and removal methods comprise poly (methylmethacrylate) (PMMA), poly-para-xylylene (Parylene™), amorphous carbon, and polystyrene, which may be removed by organic solvents, oxygen ashing, and/or low temperature (˜200° C.) oxidation, and norbornene-based materials such as BF Goodrich's Unity Sacrificial Polymer™, which may be removed by low temperature (350°-400° C.) thermal decomposition into volatiles. In the case of the Unity material, the volatile decomposition by-product actually diffuses through the bridge layer, as demonstrated by Kohl et al., Electrochemical and Solid-State Letters 1 49 (1998) for structures comprising SiO2 (500 nm) bridge layers deposited by a low temperature plasma enhanced chemical vapor deposition (PECVD) process.
In all these cases, the removal medium, (plasma, a wet chemical, or SPH material), is required to diffuse through the semi-permeable bridge layer. This is generally very difficult to achieve.
Lee et al., U.S. Pat. No. 6,228,763 teach the use of spacers to form air-gaps adjacent to metal structures in an interconnect scheme. However, in their structure, they claim that the nature of their scheme ensures that the metal structure is curved outward since it closely follows the contours of the spacer. This is an undesirable structure since it could lead to high field concentrations around the curved parts and poor breakdown behavior of the interconnect, a significant drawback. In addition, they propose the use of a single damascene scheme to form their structure. This makes their scheme very expensive and limits the performance due to their inability to extend the air-gap below the trench to obtained increased performance. Finally, in their scheme, they use plasma based methods to remove the dielectric spacer to form the air-gap and they do this with the metal interconnect already present in the structure which could lead to a degradation of the conductive properties of the interconnect.
Lee et al., U.S. Pat. No. 6,329,279 solve one of the problems they encounter in U.S. Pat. No. 6,228,763, namely the high field concentrations around the curved parts of the top of the metal line by means of a new structure; however, their gap is narrowest adjacent to the top of the metal line where it is most desirable to reduce the dielectric constant due to the presence of the relatively high k barrier layer immediately above it. The other drawbacks mentioned above for U.S. Pat. No. 6,228,763 still remain, the chief of which is that this is based on a single damascene integration scheme which is prohibitively expensive, limited in performance, and not extendible readily to any interconnect scheme in the industry which uses Cu based metallurgy.
Geffken et al., United States Patent Publication 2005/0067673 A1, also teach a method to obtain air-gaps, but indicate a drawback by noting “that since these second spacers have reduced the size of the trench openings 56, 58 and via openings 52, 54, then initially formed, the trench and via photo needs to be exposed and etched larger by about two times the spacer width.” (Geffken et al. par. [0025]). This is very difficult to achieve, especially as the structure gets closer to the tens of nanometer dimensions because this calls for a lithography process where the pitch remains the same but the openings are enlarged by twice the spacer width which makes the lithography process difficult to employ. In addition, due to the lack of a gap below
the trench and adjacent to the vias, their performance gain is limited. Finally, since their invention calls for an extra lithography step, in addition to extra wet/SC CO2 etches to remove the damaged dielectric, it is very expensive to practice.
Another concern with air-gap based dielectric structures compared to structures with solid dielectrics is that air-gap based structures have lower thermal conductivity, reduced strength, and higher permeability to moisture and oxygen. Workable schemes for incorporating air-gaps into interconnect structures must take these limitations into account.
In addition structures with air-gaps may not be as uniformly planar as structures built with intrinsically more rigid solid dielectrics. This can be a problem if locally depressed areas are formed by bridge layer sag over unsupported air-gaps, since metal filling these depressed areas will remain in the structure after chemical-mechanical polishing (CMP) and be a source of shorts and/or extra capacitance.
In view of these drawbacks with the prior art processes, there is a continued need for developing a new and improved method by which air-gaps can be formed in an interconnect to minimize or eliminate these problems.
While all of the foregoing provide advancements in the fabrication of air-gaps in semiconductor chips or semiconductor arrays or wafers or IC circuits, collectively referred to hereafter as electronic devices, there is still a need for improved or novel processes, articles of manufacture and products produced by novel processes that provide air-gap structures that eliminate or minimize these and other problems encountered in the art.